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Gate oxide

Gate oxide at NPNP transistor made by Frosch and Derrick, 1957[1]

The gate oxide is the dielectric layer that separates the gate terminal of a MOSFET (metal–oxide–semiconductor field-effect transistor) from the underlying source and drain terminals as well as the conductive channel that connects source and drain when the transistor is turned on. Gate oxide is formed by thermal oxidation of the silicon of the channel to form a thin (5 - 200 nm) insulating layer of silicon dioxide. The insulating silicon dioxide layer is formed through a process of self-limiting oxidation, which is described by the Deal–Grove model. A conductive gate material is subsequently deposited over the gate oxide to form the transistor. The gate oxide serves as the dielectric layer so that the gate can sustain as high as 1 to 5 MV/cm transverse electric field in order to strongly modulate the conductance of the channel.

Above the gate oxide is a thin electrode layer made of a conductor which can be aluminium, a highly doped silicon, a refractory metal such as tungsten, a silicide (TiSi, MoSi2, TaSi or WSi2) or a sandwich of these layers. This gate electrode is often called "gate metal" or "gate conductor". The geometrical width of the gate conductor electrode (the direction transverse to current flow) is called the physical gate width. The physical gate width may be slightly different from the electrical channel width used to model the transistor as fringing electric fields can exert an influence on conductors that are not immediately below the gate.

he electrical properties of the gate oxide are critical to the formation of the conductive channel region below the gate. In NMOS-type devices, the zone beneath the gate oxide is a thin n-type inversion layer on the surface of the p-type semiconductor substrate. It is induced by the oxide electric field from the applied gate voltage VG. This is known as the inversion channel. It is the conduction channel that allows the electrons to flow from the source to the drain.[2]

Overstressing the gate oxide layer, a common failure mode of MOS devices, may lead to gate rupture or to stress induced leakage current.

During manufacturing by reactive-ion-etching the gate oxide may damaged by antenna effect.

History

In 1955 Carl Frosch and Lincoln Derrick accidentally grew an oxide layer over silicon at Bell Labs and patented their method.[3] By 1957 Frosch and Derrick were aware of surface passivation by silicon dioxide and made the first gate oxide for a transistors.[4] In 1987, Bijan Davari led a research team at the IBM Thomas J. Watson Research Center that demonstrated the first MOSFET with a 10 nm gate oxide thickness, using tungsten gate technology.[5]

See also

References

  1. ^ Frosch, C. J.; Derick, L (1957). "Surface Protection and Selective Masking during Diffusion in Silicon". Journal of the Electrochemical Society. 104 (9): 547. doi:10.1149/1.2428650.
  2. ^ Fundamentals of Solid-State Electronics, Chih-Tang Sah. World Scientific, first published 1991, reprinted 1992, 1993 (pbk), 1994, 1995, 2001, 2002, 2006, ISBN 981-02-0637-2. -- ISBN 981-02-0638-0 (pbk).
  3. ^ US2802760A, Lincoln, Derick & Frosch, Carl J., "Oxidation of semiconductive surfaces for controlled diffusion", issued 1957-08-13 
  4. ^ Frosch, C. J.; Derick, L (1957). "Surface Protection and Selective Masking during Diffusion in Silicon". Journal of the Electrochemical Society. 104 (9): 547. doi:10.1149/1.2428650.
  5. ^ Davari, Bijan; Ting, Chung-Yu; Ahn, Kie Y.; Basavaiah, S.; Hu, Chao-Kun; Taur, Yuan; Wordeman, Matthew R.; Aboelfotoh, O. (1987). "Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide". 1987 Symposium on VLSI Technology. Digest of Technical Papers: 61–62.
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